~ruther/verilog-riscv-semestral-project

ref: bc02aba5f50d84e93657a0601f713d990ecb8f11 verilog-riscv-semestral-project/src d--------- 
fix: make rd1, rd2 in register_file regs

feat: add instruction decoder

chore: formatting

feat: add basic ram, alu, and register file
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