~ruther/verilog-riscv-semestral-project

ref: 9f4ac4dc09c9ccb93c6b1d9726bc7543ff09de00 verilog-riscv-semestral-project/Makefile -rwxr-xr-x 1.4 KiB 
fix(Makefile): make objdump and all testbenches work

chore: add makefile for both verilog and c