~ruther/verilog-riscv-semestral-project

ref: cc87c7b82949ca7374bdb56b33b7bdbdfb9e8d5c verilog-riscv-semestral-project/Makefile -rwxr-xr-x 1.4 KiB 
fix(Makefile): make objdump and all testbenches work

chore: add makefile for both verilog and c
Do not follow this link