~ruther/verilog-riscv-semestral-project: Makefile cc87c7b82949ca7374bdb56b33b7bdbdfb9e8d5c

~ruther/verilog-riscv-semestral-project

ref: cc87c7b82949ca7374bdb56b33b7bdbdfb9e8d5c verilog-riscv-semestral-project/Makefile -rwxr-xr-x 1.4 KiB

cc87c7b8 — Rutherther 2 years ago

fix(Makefile): make objdump and all testbenches work

707b5bfc — Rutherther 2 years ago

chore: add makefile for both verilog and c