~ruther/verilog-riscv-semestral-project

ref: 914e69e6c0df1f4e3f33718891c838e42fe535b1 verilog-riscv-semestral-project/src/control_unit.sv -rwxr-xr-x 3.3 KiB 
Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline
feat: implement pipeline

fix: lui, force rs1 zero, always add

feat: implement ebreak

Breaks the processor, can
exit the testcase

feat: implement sb, sh, lb, lh support via masking

fix: make sure alu is zeroed on memory load, write, jump

fix: force alu operation to addition for storing memory and pc

fix: propagate conditional jump from control_unit

feat: add control_unit wrapper over instruction_decoder
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