~ruther/verilog-riscv-semestral-project: src e3c95ad31853db8d3df0f933168a2f8ad6dd370c

~ruther/verilog-riscv-semestral-project

ref: e3c95ad31853db8d3df0f933168a2f8ad6dd370c verilog-riscv-semestral-project/src d---------

e3c95ad3 — Rutherther 2 years ago

feat: add instruction decoder

51a684d9 — Rutherther 2 years ago

chore: formatting

8adc02d7 — Rutherther 2 years ago

feat: add basic ram, alu, and register file