~ruther/verilog-riscv-semestral-project

ref: 586cf7122913dbe1faece5e92b9da4bfc0d36403 verilog-riscv-semestral-project/src/cpu.sv -rwxr-xr-x 3.5 KiB
chore: clearer naming
fix: jumping should flush two registers
feat: move jumping to execute stage
Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline
docs: better document the stage code, organize it better
feat: implement pipeline
feat: implement ebreak

Breaks the processor, can
exit the testcase
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.
fix: jump according to zero flag, not LSB zero!!
feat: implement sb, sh, lb, lh support via masking
fix: remove duplicit instruction and pc in cpu
refactor: move memory out of cpu

The cpu will have external memory,
that will allow for better testing
capabilities, and also makes more
sense.
feat: add cpu top level entity
Do not follow this link