~ruther/verilog-riscv-semestral-project

ref: 586cf7122913dbe1faece5e92b9da4bfc0d36403 verilog-riscv-semestral-project/src d---------
586cf712 — Rutherther chore: clearer naming 1 year, 3 months ago
..
-rwxr-xr-x
alu.sv
1.0 KiB
-rwxr-xr-x
control_unit.sv
3.3 KiB
-rwxr-xr-x
cpu.sv
3.5 KiB
-rw-r--r--
cpu_singlecycle.sv
4.2 KiB
-rwxr-xr-x
cpu_types.sv
1.8 KiB
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file_program_memory.sv
319 bytes
-rw-r--r--
forwarder.sv
1.2 KiB
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instruction_decoder.sv
7.1 KiB
-rwxr-xr-x
program_counter.sv
383 bytes
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ram.sv
1.1 KiB
-rwxr-xr-x
register_file.sv
828 bytes
d---------
stages/
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