~ruther/verilog-riscv-semestral-project

ref: 308a146292087449ecb82e4b7935f789ab21c64b verilog-riscv-semestral-project/Makefile -rwxr-xr-x 2.2 KiB 
feat: add support for official tests

feat: pass program to execute by parameter

chore: trace memory array

fix(Makefile): make objdump and all testbenches work

chore: add makefile for both verilog and c