~ruther/verilog-riscv-semestral-project

ref: 1d7c9233527974f1bfd8db7e0027d5871911b997 verilog-riscv-semestral-project/src/register_file.sv -rwxr-xr-x 828 bytes
37437a00 — Rutherther 2 years ago
chore: remove first unused register
0e23dce5 — Rutherther 2 years ago
fix(register_file): output register if addr not zero
24eccbe0 — Rutherther 2 years ago
refactor: parametrize register file
69ced879 — Rutherther 2 years ago
fix: make rd1, rd2 in register_file regs
51a684d9 — Rutherther 2 years ago
chore: formatting
8adc02d7 — Rutherther 2 years ago
feat: add basic ram, alu, and register file