~ruther/verilog-riscv-semestral-project

ref: 18eeb2c56b849ad7bffa04c2e212619237449216 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 1.0 KiB 
feat: add support for loading and saving ram from disk

feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.

fix: offset ram by bytes, not bits

feat: implement sb, sh, lb, lh support via masking

feat: add basic ram, alu, and register file