~ruther/verilog-riscv-semestral-project

ref: 18eeb2c56b849ad7bffa04c2e212619237449216 verilog-riscv-semestral-project/src d---------
18eeb2c5 — Rutherther tests: compile only once, copy proram, memory files to correct locations 1 year, 6 months ago
..
-rwxr-xr-x
alu.sv
1.0 KiB
-rwxr-xr-x
control_unit.sv
3.2 KiB
-rwxr-xr-x
cpu.sv
4.2 KiB
-rwxr-xr-x
cpu_types.sv
368 bytes
-rwxr-xr-x
file_program_memory.sv
319 bytes
-rwxr-xr-x
instruction_decoder.sv
7.0 KiB
-rwxr-xr-x
program_counter.sv
383 bytes
-rwxr-xr-x
ram.sv
1.0 KiB
-rwxr-xr-x
register_file.sv
828 bytes
Do not follow this link