~ruther/verilog-riscv-semestral-project

ref: 32388b786d96e16d5264fe541d217ba5ca6b7084 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 1.0 KiB
32388b78 — Rutherther 2 years ago
feat: add support for loading and saving ram from disk
a400aceb — Rutherther 2 years ago
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.
ca9604e2 — Rutherther 2 years ago
fix: offset ram by bytes, not bits
acf0f724 — Rutherther 2 years ago
feat: implement sb, sh, lb, lh support via masking
8adc02d7 — Rutherther 2 years ago
feat: add basic ram, alu, and register file