~ruther/verilog-riscv-semestral-project

ref: 18eeb2c56b849ad7bffa04c2e212619237449216 verilog-riscv-semestral-project/src/control_unit.sv -rwxr-xr-x 3.2 KiB
c682cc06 — Rutherther 2 years ago
feat: implement ebreak

Breaks the processor, can
exit the testcase
acf0f724 — Rutherther 2 years ago
feat: implement sb, sh, lb, lh support via masking
bc02aba5 — Rutherther 2 years ago
fix: make sure alu is zeroed on memory load, write, jump
02405eec — Rutherther 2 years ago
fix: force alu operation to addition for storing memory and pc
e44bfc9e — Rutherther 2 years ago
fix: propagate conditional jump from control_unit
52b05e5d — Rutherther 2 years ago
feat: add control_unit wrapper over instruction_decoder