~ruther/verilog-riscv-semestral-project: Makefile 11422de00c50854a650da69469f3646f4e2f500b

~ruther/verilog-riscv-semestral-project

ref: 11422de00c50854a650da69469f3646f4e2f500b verilog-riscv-semestral-project/Makefile -rwxr-xr-x 1.5 KiB

5fe03098 — Rutherther 3 years ago

chore: trace memory array

cc87c7b8 — Rutherther 3 years ago

fix(Makefile): make objdump and all testbenches work

707b5bfc — Rutherther 3 years ago

chore: add makefile for both verilog and c