~ruther/verilog-riscv-semestral-project

ref: 0a9a14b7e6d78454c80c2331b0bd0150bc18d631 verilog-riscv-semestral-project/Makefile -rwxr-xr-x 1.4 KiB
cc87c7b8 — Rutherther 2 years ago 
fix(Makefile): make objdump and all testbenches work
707b5bfc — Rutherther 2 years ago 
chore: add makefile for both verilog and c