~ruther/verilog-riscv-semestral-project (0a9a14b7e6d78454c80c2331b0bd0150bc18d631): / - ditigal.xyz git

~ruther/verilog-riscv-semestral-project

0a9a14b7 — Rutherther test: add ram test 1 year, 7 months ago

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.envrc

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.gitignore

90 bytes

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Makefile

1.4 KiB

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flake.lock

1.5 KiB

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flake.nix

1.3 KiB

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programs/

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src/

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testbench/

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