~ruther/verilog-riscv-semestral-project: Makefile 057ee98bbecfb8a284b67bef50b04b70ae18e220

~ruther/verilog-riscv-semestral-project

ref: 057ee98bbecfb8a284b67bef50b04b70ae18e220 verilog-riscv-semestral-project/Makefile -rwxr-xr-x 1.4 KiB

cc87c7b8 — Rutherther 3 years ago

fix(Makefile): make objdump and all testbenches work

707b5bfc — Rutherther 3 years ago

chore: add makefile for both verilog and c