~ruther/verilog-riscv-semestral-project

ref: 057ee98bbecfb8a284b67bef50b04b70ae18e220 verilog-riscv-semestral-project/Makefile -rwxr-xr-x 1.4 KiB 
fix(Makefile): make objdump and all testbenches work

chore: add makefile for both verilog and c
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