~ruther/vhdl-spi-2

ref: abfea28a8a2555ec22557089a359b3f2b6fd5f23 vhdl-spi-2/hdl_spi/models d---------
tests: add proper checks for clock polarity before and after csn
tests: properly account for soonly rising csn
feat: implement spi model narrow sck check
fix: assumptions about synthesizable code
feat: add csn pulse test and rx, tx disabling test
chore: move spi models to separate file