fix: clock polarity on csn falling and rising. Proper wait after csn falling and before csn rising

tests: add proper checks for clock polarity before and after csn

tests: fix _t meaning (tri state)

tests: fix peripheral interrupt test - wrong check for rx buffer full

fix: short last sck pulse on slower clock

tests: add spi_peripheral 'application' testcase

tests: add test for interrupts spi_peripheral

feat: add test for max divisor (256)

feat: implement spi model narrow sck check

fix: assumptions about synthesizable code

feat: add initial test for spi peripheral

feat: add test for lsbfirst

chore: remove todo comments

feat: add csn pulse test and rx, tx disabling test

feat: add tests for rx blocking

chore: move spi models to separate file

feat: add tests for clock phase, polarity

feat: tests for multiple transmissions, rx lost

chore: add ghdl support vhdl2008 arg

feat: add first basic test