1 files changed, 1 insertions(+), 0 deletions(-)

M hdl_spi/tests/Makefile

@@ 9,6 9,7 @@ SRC = $(PWD)/../src
 VHDL_SOURCES=$(SRC)/spi_pkg.vhd $(SRC)/rs_latch.vhd $(SRC)/register.vhd $(SRC)/shift_register.vhd $(SRC)/spi_clkgen.vhd $(SRC)/spi_clkmon.vhd $(SRC)/spi_multiplexor.vhd $(SRC)/spi_slave_ctrl.vhd $(SRC)/spi_master_ctrl.vhd $(SRC)/spi_master.vhd $(SRC)/spi_masterslave.vhd $(SRC)/spi_peripheral.vhd
 
 VCOM_ARGS = -2008
+GHDL_ARGS= --std=08
 
 # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
 TOPLEVEL = spi_masterslave