fix: ssd1306 logic

fix: set initial gen clk in clock divider

This is just for simulation. On FPGA, there always
has to be either one or zero...

feat: split ssd1306 counter to logic entity

fix: use synced sda, scl for master, slave entities

feat: store address, rw in address generator or detector

fix: move to bus busy on arbitration err or start condition

fix: count to 9, make i2c frequency 10 MHz

feat: simplify bcd counter

fix: make sure clock divider has 50 % duty cycle

fix: full_on skips indices

fix: many changes

fix: issues on master

fix: issues in master logic

fix: some stuff

fix: logic fixes master state

fix: address generator minor issues

fix: start stop condition generator behavior

fix: make sure scl changed after delay

fix: scl generator minor mistakes

feat: add master top entity