6 files changed, 13 insertions(+), 15 deletions(-)

M src/i2c/master.vhd
M src/i2c/master_state.vhd
M src/i2c/scl_generator.vhd
M src/i2c/tx.vhd
M tb/i2c/tb_i2c_pkg.vhd
M tb/i2c/tb_i2c_slave_pkg.vhd

@@ 35,7 35,7 @@ entity master is
     stop_i              : in  std_logic;
     start_i             : in  std_logic;
     run_i               : in  std_logic;
-    rw_o                : out std_logic;  -- 1 - read, 0 - write
+    rw_i                : in  std_logic;  -- 1 - read, 0 - write
     dev_busy_o          : out std_logic;  -- Communicating with master
     bus_busy_o          : out std_logic;  -- Bus is busy, someone else is communicating
     waiting_o           : out std_logic;  -- Waiting for data or read data


@@ 84,14 84,12 @@ architecture a1 of master is
   signal scl_gen_scl_enable : std_logic;
   signal scl_gen_req_continuous : std_logic;
 
-  signal rw : std_logic;
   signal rst_i2c : std_logic;
 
   signal scl_falling_delayed : std_logic;
   signal waiting_for_data : std_logic;
   signal scl_gen_falling : std_logic;
 begin  -- architecture a1
-  rw_o <= rw;
   dev_busy_o <= transmitting or receiving;
   bus_busy_o <= bus_busy;
   waiting_for_data <= tx_scl_stretch or rx_scl_stretch;


@@ 232,7 230,7 @@ begin  -- architecture a1
       unexpected_sda_o      => adr_unexpected_sda,
       done_o                => adr_done,
       start_i               => adr_gen_start,
-      rw_i                  => rw);
+      rw_i                  => rw_i);
 
   state_machine : entity work.master_state
     port map (


@@ 243,7 241,7 @@ begin  -- architecture a1
       start_i                  => start_i,
       stop_i                   => stop_i,
       run_i                    => run_i,
-      rw_i                     => rw,
+      rw_i                     => rw_i,
 --
       expect_ack_i             => expect_ack_i,
       noack_address_i          => adr_noack,

@@ 177,7 177,7 @@ begin  -- architecture a1
       elsif address_gen_done_i = '1' then
         if any_err = '1' then
           next_state <= GENERATING_STOP;
-        elsif rw_i = '1' then
+        elsif rw_i = '0' then
           next_state <= TRANSMITTING;
         else
           next_state <= RECEIVING;

@@ 53,8 53,8 @@ begin  -- architecture a1
 
   scl_changing <= scl_rising_i or scl_falling_i;
 
-  should_rise <= (gen_rising_i or gen_continuous_i and not gen_falling_i) and not curr_scl;
-  should_fall <= (gen_falling_i or gen_continuous_i and not gen_rising_i) and curr_scl;
+  should_rise <= (gen_rising_i or gen_continuous_i) and not gen_falling_i and not curr_scl;
+  should_fall <= (gen_falling_i or gen_continuous_i) and not gen_rising_i and curr_scl;
   should_change <= should_rise or should_fall;
   can_change <= '1' when curr_stable_count = MIN_STABLE_CYCLES else '0';
 

@@ 78,7 78,7 @@ architecture a1 of tx is
 
   signal ready : std_logic;
 begin  -- architecture a1
-  scl_stretch_o <= '1' when curr_state = WAITING_FOR_DATA else '0';
+  scl_stretch_o <= '1' when curr_state = WAITING_FOR_DATA and curr_done = '0' else '0';
   ready_o <= ready;
   sda_enable_o <= not tx_buffer(8) when curr_state = SENDING else '0';
   unexpected_sda_o <= '1' when curr_state = SENDING and sda_i /= tx_buffer(8) and scl_rising_i = '1' else '0';


@@ 184,9 184,11 @@ begin  -- architecture a1
         curr_tx_buffers_filled <= "00";
         curr_saving_buffer_index <= 0;
         curr_scl <= '1';                -- assume 1 (the default, no one transmitting)
+        curr_done <= next_done;
       elsif rst_i2c_i = '1' then
         curr_state <= IDLE;
         curr_scl <= '1';                -- assume 1 (the default, no one transmitting)
+        curr_done <= '0';
       else
         curr_state <= next_state;
         curr_tx_buffers <= next_tx_buffers;


@@ 194,6 196,7 @@ begin  -- architecture a1
         curr_tx_buffers_filled <= next_tx_buffers_filled;
         curr_saving_buffer_index <= next_saving_buffer_index;
         curr_scl <= next_scl;
+        curr_done <= next_done;
       end if;
     end if;
   end process set_regs;

@@ 161,14 161,14 @@ package body tb_i2c_pkg is
     signal sda       : in std_logic) is
   begin
     wait until rising_edge(sda) and scl = 'H' for timeout;
-    check(sda = '1' and scl = 'H', "Did not get stop condition in time.");
+    check(sda = 'H' and scl = 'H', "Did not get stop condition in time.");
   end procedure wait_for_stop_condition;
 
   procedure wait_for_scl_rise (
     constant timeout : in time;
     signal scl       : in std_logic) is
   begin
-    wait until scl = 'H' for timeout;
+    wait until rising_edge(scl) for timeout;
     check_equal(scl, 'H', "Did not get rising scl in time.");
     wait until falling_edge(clk);
   end procedure wait_for_scl_rise;


@@ 178,7 178,7 @@ package body tb_i2c_pkg is
     constant timeout : in time;
     signal scl       : in std_logic) is
   begin
-    wait until scl = '0' for timeout;
+    wait until falling_edge(scl) for timeout;
     check_equal(scl, '0', "Did not get falling scl in time.");
     wait until falling_edge(clk);
   end procedure wait_for_scl_fall;

@@ 69,14 69,12 @@ package body tb_i2c_slave_pkg is
     constant exp_ack     : in    std_logic := '1') is
 
   begin  -- procedure transmit
-    report "Start slave transmit";
     if scl = 'H' then
         wait_for_scl_fall(scl_timeout, scl);
     end if;
 
     -- data
     for i in 7 downto 0 loop
-    report "Data " & integer'image(i) & " scl is: " & std_logic'image(scl);
       wait until falling_edge(clk);
       sda <= '0' when data(i) = '0' else 'Z';
       wait_for_scl_rise(scl_timeout, scl);


@@ 87,7 85,6 @@ package body tb_i2c_slave_pkg is
     sda <= 'Z';
     wait_for_scl_rise(scl_timeout, scl);
 
-    report "Ack slave transmit";
     if exp_ack = '1' then
       check_equal(sda, '0', "No acknowledge");
     elsif exp_ack = '0' then