fix: ssd1306 logic

fix: set initial gen clk in clock divider

This is just for simulation. On FPGA, there always
has to be either one or zero...

docs: finish documentation

feat: split ssd1306 counter to logic entity

fix: use synced sda, scl for master, slave entities

docs: styling

docs: add basic documentation

chore: update flake inputs, add docs dev env

tests: fix address generator done test

feat: store address, rw in address generator or detector

fix: move to bus busy on arbitration err or start condition

feat: add libraries to vunit

fix: count to 9, make i2c frequency 10 MHz

feat: simplify bcd counter

fix: make sure clock divider has 50 % duty cycle

docs: add basic README documentation

tests: diable no_check taking long

fix: full_on skips indices

fix: many changes

chore: update constraints for master ssd1306