~ruther/vhdl-i2c: fix: set initial gen clk in clock divider

b7600b1d64f28e6c5a661cb853a0cdfbb0b0ee6c — Rutherther 1 year, 2 months ago 310fc3d

fix: set initial gen clk in clock divider

This is just for simulation. On FPGA, there always
has to be either one or zero...

patch browse .tar.gz

1 files changed, 1 insertions(+), 1 deletions(-)

M src/utils/clock_divider.vhd

M src/utils/clock_divider.vhd => src/utils/clock_divider.vhd +1 -1

@@ 18,7 18,7 @@ architecture a1 of clock_divider is
   signal curr_count : integer range 0 to MAX - 1;
   signal next_count : integer range 0 to MAX - 1;
 
-  signal gen_clk : std_logic;
+  signal gen_clk : std_logic := '0';
 begin  -- architecture a1
   keep_max_freq: if IN_FREQ = OUT_FREQ generate
     clk_o <= clk_i;