fix: logic fixes master state
feat: prepare i2c slave tb model
tests: add address generator testbench
fix: address generator minor issues
tests: add startstop condition generator testbench
fix: start stop condition generator behavior
fix: make sure scl changed after delay
tests: add test for scl generator
fix: scl generator minor mistakes
feat: add master top entity
fix: mcu slave tbs, wait for sync rst
chore: test flags for ghdl to compile
feat: synchronize reset in mcu slave tops
feat: add master state entity
feat: add address generator
feat: add start, stop condition generator
feat: add waiting output to slave
feat: add done fields to tx, rx
tests(mcu): count correctly, excluding the address