~ruther/verilog-riscv-semestral-project

verilog-riscv-semestral-project/testbench/tb_cpu_simple.sv -rw-r--r-- 2.5 KiB
79c7be5c — Rutherther 2 years ago main
chore: remove unnecessary executable flags

Closes #4.
73cf8a16 — Rutherther 2 years ago
tests: fix simple cpu test to use memory.dump and doesnt wait for ebreak
c682cc06 — Rutherther 2 years ago
feat: implement ebreak

Breaks the processor, can
exit the testcase
a400aceb — Rutherther 2 years ago
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.
707b5bfc — Rutherther 2 years ago
chore: add makefile for both verilog and c
acf0f724 — Rutherther 2 years ago
feat: implement sb, sh, lb, lh support via masking
773f4b99 — Rutherther 2 years ago
test: add simple cpu test