~ruther/verilog-riscv-semestral-project

ref: 79c7be5c1c8ae2aea07f48d32abca650d24e8045 verilog-riscv-semestral-project/testbench/tb_cpu_simple.sv -rw-r--r-- 2.5 KiB 
chore: remove unnecessary executable flags

Closes #4.

tests: fix simple cpu test to use memory.dump and doesnt wait for ebreak

feat: implement ebreak

Breaks the processor, can
exit the testcase

feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.

chore: add makefile for both verilog and c

feat: implement sb, sh, lb, lh support via masking

test: add simple cpu test
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