~ruther/verilog-riscv-semestral-project

verilog-riscv-semestral-project/src/stages/execute.sv -rw-r--r-- 2.0 KiB
914e69e6 — Rutherther 2 years ago
refactor: save pc + 4 in stages
586cf712 — Rutherther 2 years ago
chore: clearer naming
66d14163 — Rutherther 2 years ago
feat: move jumping to execute stage
f8e4e3ed — Rutherther 2 years ago
Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline
docs: better document the stage code, organize it better
489df849 — Rutherther 2 years ago
chore: import cpu types in stages
89310129 — Rutherther 2 years ago
feat: implement pipeline