5 files changed, 7 insertions(+), 2 deletions(-)

M src/cpu.sv
M src/cpu_types.sv
M src/stages/decode.sv
M src/stages/execute.sv
M src/stages/fetch.sv

@@ 70,7 70,7 @@ module cpu(
     else if (jump)
       pc_next = jumping_pc_next;
     else // assume no jump. If jump, if result will be thrown out
-      pc_next = pc + 4;
+      pc_next = fetch_out.pc_plus_4;
   end
 
   // data for forwarding from the stages

@@ 56,6 56,7 @@ package cpu_types;
     register_data_status_t data;
 
     bit [31:0] pc;
+    bit [31:0] pc_plus_4;
 
     bit [31:0] reg_rs1;
     bit [31:0] reg_rs2;

@@ 36,6 36,7 @@ module decode(
   assign stage_out.data.valid = 0; // the data cannot be valid at this point;
 
   assign stage_out.pc = stage_in.pc;
+  assign stage_out.pc_plus_4 = stage_in.pc_plus_4;
 
   assign stage_out.instruction.reg_we = reg_we;
 

@@ 16,11 16,12 @@ module execute(
 
   assign stage_out.instruction = stage_in.instruction;
   assign stage_out.pc = stage_in.pc;
+  assign stage_out.pc_plus_4 = stage_in.pc_plus_4;
   assign stage_out.reg_rs1 = stage_in.reg_rs1;
   assign stage_out.reg_rs2 = stage_in.reg_rs2;
 
   assign stage_out.data.target = stage_in.valid ? stage_in.data.target : 0;
-  assign stage_out.data.value = stage_in.instruction.reg_rd_src == RD_PC_PLUS ? stage_in.pc + 4 : alu_out;
+  assign stage_out.data.value = stage_in.instruction.reg_rd_src == RD_PC_PLUS ? stage_in.pc_plus_4 : alu_out;
   assign stage_out.data.valid = stage_in.valid && (stage_in.instruction.reg_rd_src != RD_MEMORY);
 
   assign stage_out.valid = stage_in.valid;

@@ 9,7 9,9 @@ module fetch(
   output       stage_status_t stage_out
 );
   assign stage_out.instruction.instruction = mem_instruction;
+
   assign stage_out.pc = pc;
+  assign stage_out.pc_plus_4 = pc + 4;
 
   assign stage_out.valid = !flush;
   assign stage_out.ready = 1;