~ruther/verilog-riscv-semestral-project: src/register_file.sv f8bf441ea1e4cf7b0e609b80aecca786fa2a48f3

~ruther/verilog-riscv-semestral-project

ref: f8bf441ea1e4cf7b0e609b80aecca786fa2a48f3 verilog-riscv-semestral-project/src/register_file.sv -rwxr-xr-x 593 bytes

69ced879 — Rutherther 1 year, 7 months ago

fix: make rd1, rd2 in register_file regs

51a684d9 — Rutherther 1 year, 8 months ago

chore: formatting

8adc02d7 — Rutherther 1 year, 8 months ago

feat: add basic ram, alu, and register file