~ruther/verilog-riscv-semestral-project

ref: f8bf441ea1e4cf7b0e609b80aecca786fa2a48f3 verilog-riscv-semestral-project/src/register_file.sv -rwxr-xr-x 593 bytes
f8bf441e — Rutherther chore: move default case 1 year, 7 months ago
                                                                                
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module register_file(clk, a1, a2, a3, we3, wd3, rd1, rd2);

  input clk;
  input [4:0] a1;
  input [4:0] a2;
  input [4:0] a3;

  input       we3; // write enable
  input [31:0] wd3; // write data

  output reg [31:0] rd1;
  output reg [31:0] rd2;

  reg [31:0]    gprs [32];

  wire          clk;

  always_comb begin
    if (a1 == 5'b0)
      rd1 = gprs[a1];
    else
      rd1 = 32'b0;
  end

  always_comb begin
    if (a2 == 5'b0)
      rd2 = gprs[a2];
    else
      rd2 = 32'b0;
  end

  always_ff @(posedge clk) begin
    if (we3 && a3 != 5'b0)
      gprs[a3] <= wd3;
  end

endmodule
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