~ruther/verilog-riscv-semestral-project: Makefile e7b5d989532b0690f2b0ef3a1b7a0072903c0d51

~ruther/verilog-riscv-semestral-project

ref: e7b5d989532b0690f2b0ef3a1b7a0072903c0d51 verilog-riscv-semestral-project/Makefile -rwxr-xr-x 1.4 KiB

cc87c7b8 — Rutherther 2 years ago

fix(Makefile): make objdump and all testbenches work

707b5bfc — Rutherther 2 years ago

chore: add makefile for both verilog and c