~ruther/verilog-riscv-semestral-project

ref: df876b38b787b7f1e9120775311a0b1a17e2758b verilog-riscv-semestral-project/programs d---------
chore: load gcd parameters from memory
chore: move inital sp to 1020
feat: store c results in memory addr 0
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.
feat: add gcd program for testing
feat: add branches.c test
chore: remove gcc generated file
feat: add basic testing programs
Do not follow this link