~ruther/verilog-riscv-semestral-project

ref: ca9604e2c8a9c44ccba5223ef095d84cd618bbe1 verilog-riscv-semestral-project/src/instruction_decoder.sv -rwxr-xr-x 6.9 KiB
acf0f724 — Rutherther 2 years ago
feat: implement sb, sh, lb, lh support via masking
2867e246 — Rutherther 2 years ago
fix: do not set subtract for non-R instructions
2f09f768 — Rutherther 2 years ago
fix: make immediates sign extended
27fcb8d9 — Rutherther 2 years ago
fix: do not use immediate in alu src for SB
32ebeea6 — Rutherther 2 years ago
feat(decoder): implement memory mask, conditional jumps
e3c95ad3 — Rutherther 2 years ago
feat: add instruction decoder