~ruther/verilog-riscv-semestral-project (ca9604e2c8a9c44ccba5223ef095d84cd618bbe1): / - ditigal.xyz git

~ruther/verilog-riscv-semestral-project

ca9604e2 — Rutherther fix: offset ram by bytes, not bits 1 year, 7 months ago

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.envrc

10 bytes

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.gitignore

52 bytes

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Makefile

1.4 KiB

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flake.lock

1.5 KiB

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flake.nix

1.1 KiB

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programs/

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src/

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testbench/

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