~ruther/verilog-riscv-semestral-project

ref: ca9604e2c8a9c44ccba5223ef095d84cd618bbe1 verilog-riscv-semestral-project/src/control_unit.sv -rwxr-xr-x 3.1 KiB 
feat: implement sb, sh, lb, lh support via masking

fix: make sure alu is zeroed on memory load, write, jump

fix: force alu operation to addition for storing memory and pc

fix: propagate conditional jump from control_unit

feat: add control_unit wrapper over instruction_decoder
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