~ruther/verilog-riscv-semestral-project

feat(decoder): implement memory mask, conditional jumps
refactor: parametrize register file
chore: move default case
fix: make rd1, rd2 in register_file regs
feat: add instruction decoder
chore: formatting
feat: add basic ram, alu, and register file
chore: add gitignore
chore: add flake environment
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