~ruther/verilog-riscv-semestral-project: Makefile bb32d2ddcd68d2cf131760d9c1d99f9107c912f8

~ruther/verilog-riscv-semestral-project

ref: bb32d2ddcd68d2cf131760d9c1d99f9107c912f8 verilog-riscv-semestral-project/Makefile -rwxr-xr-x 1.4 KiB

cc87c7b8 — Rutherther 2 years ago

fix(Makefile): make objdump and all testbenches work

707b5bfc — Rutherther 2 years ago

chore: add makefile for both verilog and c