~ruther/verilog-riscv-semestral-project: Makefile adfdc041e204e13c59c32d866fb2ee288b272c57

~ruther/verilog-riscv-semestral-project

ref: adfdc041e204e13c59c32d866fb2ee288b272c57 verilog-riscv-semestral-project/Makefile -rwxr-xr-x 1.4 KiB

cc87c7b8 — Rutherther 2 years ago

fix(Makefile): make objdump and all testbenches work

707b5bfc — Rutherther 2 years ago

chore: add makefile for both verilog and c