~ruther/verilog-riscv-semestral-project

ref: a6f4c7fc1c66f05cd78d52e8e3b9229ae58ef2f7 verilog-riscv-semestral-project/tests/custom/custom_tests.py -rwxr-xr-x 1.9 KiB 
tests: add more custom tests

tests: add register dump, printing

feat: add support for official tests
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