~ruther/verilog-riscv-semestral-project (a6f4c7fc1c66f05cd78d52e8e3b9229ae58ef2f7): / - ditigal.xyz git

~ruther/verilog-riscv-semestral-project

a6f4c7fc — Rutherther chore: add new files to compilation list 1 year, 5 months ago

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.envrc

10 bytes

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.gitignore

110 bytes

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.gitmodules

137 bytes

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Makefile

2.6 KiB

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README.md

2.8 KiB

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flake.lock

1.5 KiB

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flake.nix

1.1 KiB

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programs/

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src/

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testbench/

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tests/

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