~ruther/verilog-riscv-semestral-project

ref: a400aceb574400fad6b269927793a5c13aab647c verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 554 bytes
feat: make RAM word aligned, add byte_enable

Support sb, sh, lb, lh using byte enable
instead of non-word aligned reads and writes.
fix: offset ram by bytes, not bits
feat: implement sb, sh, lb, lh support via masking
feat: add basic ram, alu, and register file
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