~ruther/verilog-riscv-semestral-project (a400aceb574400fad6b269927793a5c13aab647c): / - ditigal.xyz git

~ruther/verilog-riscv-semestral-project

a400aceb — Rutherther feat: make RAM word aligned, add byte_enable 1 year, 5 months ago

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.envrc

10 bytes

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.gitignore

90 bytes

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Makefile

1.4 KiB

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flake.lock

1.5 KiB

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flake.nix

1.3 KiB

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programs/

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src/

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testbench/

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