~ruther/verilog-riscv-semestral-project

ref: a400aceb574400fad6b269927793a5c13aab647c verilog-riscv-semestral-project/src d---------
a400aceb — Rutherther feat: make RAM word aligned, add byte_enable 2 years ago
..
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alu.sv
1.0 KiB
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control_unit.sv
3.1 KiB
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cpu.sv
4.1 KiB
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cpu_types.sv
368 bytes
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file_program_memory.sv
328 bytes
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instruction_decoder.sv
6.9 KiB
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program_counter.sv
383 bytes
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ram.sv
554 bytes
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register_file.sv
824 bytes