~ruther/verilog-riscv-semestral-project: programs 9f4ac4dc09c9ccb93c6b1d9726bc7543ff09de00

~ruther/verilog-riscv-semestral-project

ref: 9f4ac4dc09c9ccb93c6b1d9726bc7543ff09de00 verilog-riscv-semestral-project/programs d---------

adfdc041 — Rutherther 2 years ago

feat: add branches.c test

6ce1c838 — Rutherther 2 years ago

chore: remove gcc generated file

30a7f949 — Rutherther 2 years ago

feat: add basic testing programs