~ruther/verilog-riscv-semestral-project: programs adfdc041e204e13c59c32d866fb2ee288b272c57

~ruther/verilog-riscv-semestral-project

ref: adfdc041e204e13c59c32d866fb2ee288b272c57 verilog-riscv-semestral-project/programs d---------

adfdc041 — Rutherther 2 years ago

feat: add branches.c test

6ce1c838 — Rutherther 2 years ago

chore: remove gcc generated file

30a7f949 — Rutherther 2 years ago

feat: add basic testing programs