~ruther/verilog-riscv-semestral-project: .gitignore 9f4ac4dc09c9ccb93c6b1d9726bc7543ff09de00

~ruther/verilog-riscv-semestral-project

ref: 9f4ac4dc09c9ccb93c6b1d9726bc7543ff09de00 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 90 bytes

057ee98b — Rutherther 2 years ago

chore: add generated bin, obj gitignore files

65ab00a4 — Rutherther 2 years ago

chore: ignore obj_dir, vcd outputs

9c81ece2 — Rutherther 2 years ago

chore: add gitignore