~ruther/verilog-riscv-semestral-project

ref: 9f4ac4dc09c9ccb93c6b1d9726bc7543ff09de00 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 90 bytes
9f4ac4dc — Rutherther fix: jump according to zero flag, not LSB zero!! 2 years ago 
                                                                                
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.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd

waves/
programs/bin/
*.o
*.bin
*.dat