~ruther/verilog-riscv-semestral-project: .gitignore 057ee98bbecfb8a284b67bef50b04b70ae18e220

~ruther/verilog-riscv-semestral-project

ref: 057ee98bbecfb8a284b67bef50b04b70ae18e220 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 90 bytes

057ee98b — Rutherther 1 year, 10 months ago

chore: add generated bin, obj gitignore files

65ab00a4 — Rutherther 1 year, 10 months ago

chore: ignore obj_dir, vcd outputs

9c81ece2 — Rutherther 1 year, 10 months ago

chore: add gitignore