~ruther/verilog-riscv-semestral-project

ref: 914e69e6c0df1f4e3f33718891c838e42fe535b1 verilog-riscv-semestral-project/src/stages/decode.sv -rw-r--r-- 3.0 KiB 
refactor: save pc + 4 in stages

chore: clearer naming

fix: jumping should flush two registers

feat: move jumping to execute stage

Merge pull request #1 from Rutherther/feat/pipeline

Implement pipeline
docs: better document the stage code, organize it better

feat: add forwarding signal for better debugging

feat: implement pipeline
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